European Symposium on Research in Computer Security (ESORICS) Business Cat: Effects of Quality of Service Features on Side Channels in AMD SEV-SNP
Usenix Security Symposium (USENIX-Security) Spectre on RISC-V Silicon: Attacks and Defenses on Commercial Out-of-Order Processors
Usenix Security Symposium (USENIX-Security) InstrSem: Automatically and Generically Inferring Semantics of (Undocumented) CPU Instructions
IEEE Symposium on Security and Privacy (S&P) RISCy Cache Coherence: Timer-Free Architectural Cache Attacks via Instruction/Data Cache Incoherence
IEEE Symposium on Security and Privacy (S&P) TDXRay: Microarchitectural Side-Channel Analysis of Intel TDX for Real-World Workloads
